The present invention relates to an electrically programmable and erasable semiconductor nonvolatile memory device, and more particularly to a semiconductor nonvolatile memory device in which it is arranged so that continuation and suspension of the programming and program-verify sequence performed at time of reprogramming can be detected and controlled automatically in the memory device, thus making it possible to make reprogramming operation and program-verify operation high in speed and to miniaturize the device thereof.
A reprogramming circuit structure of a NAND-EEPROM system has been heretofore proposed in Symposium on VLSI Circuits Digest of Technical Papers pp. 20-21 1992 as a method of electrically reprogramming data of a plurality of nonvolatile semiconductor memory elements (memory cells) control gates of which are connected to the same word line at the same time. FIG. 22, FIG. 23 and FIG. 24 are for explaining the conventional example described above.
FIG. 22 shows a reprogramming circuit structure of a conventional NAND-EEPROM. Two gate input terminals of a read/write circuit are connected to data lines BLai and BLbi of different memory arrays through verify circuits. The read/write circuit is composed of a flip-flop type, and this circuit acts as a differential sense circuit at time of program-verify operation and acts as a data latch circuit at time of programming operation.
When data are loaded at the same time in a plurality of memory cells on word lines, threshold voltages of individual memory cells have to be arranged within a certain predetermined positive voltage range. So, the threshold voltages of the memory cells on the word line are read out (verify operation) after performing programming operation, thus determining whether the threshold voltages are within a predetermined positive range with respect to all memory cells in which programming is made. When the threshold voltage is out of the range, programming operation has been repeated until the threshold voltage is reinstated in the range.
In the NAND-EEPROM, the threshold voltage of the memory cell shows a low voltage state (a negative threshold voltage) by erase operation and shows a high voltage state (a positive threshold voltage) by programming operation. The programming operation is performed by applying 18V to a selected word line, applying 0V to a data line with respect to the memory cell to which programming is made (selected) and applying 8V to the data line with respect to the memory cell in which programming is not made (unselected). Besides, the loaded data are held in a latch in the read/write circuit, and 8V for the unselected data line is obtained by boosting the voltage of a terminal Vrw of the read/write circuit up to 8V.
After completing programming described above, program-verify is made using a verify circuit. A signal timing waveform diagram at time of program-verify operation is shown in FIG. 23. Now, when a cell on the side of the memory cell array (a) has been selected, the voltage of the bit lines BLai is precharged by .phi.pa up to voltage Va=(3/5) Vcc, i.e., 1.8V. On the other hand, the voltage of the dummy bit lines of the bit lines BLbi is precharged by .phi.pb up to Vb=(1/2) Vcc, i.e., 1.5V (t1 to t2).
After the bit lines are precharged, the voltage of the selected word line (CG) is dropped down to the program-verify voltage 0.6V, and Vcc is applied to the unselected word line (CG). In case the threshold voltage of the selected memory cell is at 0.6V or below, an electric current flows in the selected memory cell, and the voltage of the bit line shows 1.5V or below. On the other hand, when the threshold voltage of the memory cell is higher than 0.6V, no electric current flows, and the voltage of the bit lines is maintained at the precharge voltage of 1.8V (t2 to t3).
When all word lines (CG) are brought into an unselected state thereafter, a verify circuit signal .phi.av shows an active state (Vcc). When latched data of the read/write circuit show "1" (voltage value 0V), a MOS transistor T1 is turned OFF, and the voltage of the bit lines BLai is maintained at a level before .phi.av is brought into an active state. On the other hand, when the latch data show "0" (voltage value Vcc), the MOS transistor T1 is turned ON, and the voltage of the bit lines BLai shows 1.5V or higher (t3 to t4).
When the verify circuit signal .phi.av turns low (Vss), the read/write circuit is brought into an equalized state (.phi.p: high, .phi.n: low, .phi.e: high), and it is operated thereafter as a data hold circuit by activation of the verify circuit signals .phi.a and .phi.b (t4 and thereafter).
The voltage of the bit lines BLai is read by an open-bit line architecture, and read-out (program-verify) data after programming thereof are reprogrammed into the latch data of the read/write circuit. The relationship among programmed data, reprogrammed data and data of memory cells is shown in FIG. 24.
Now, when a certain memory cell is applied with "1" (latch data voltage 0V) programming and the threshold voltage of the memory cell reaches a value of 0.6V or higher in program-verify operation, the latch data voltage is applied with Vcc, i.e., "0" programming in order to prevent over programming of the memory cell.
In the prior art described above, the programming and program-verify sequence has been controlled for each bit of a reprogrammed sector. Since detection and determination on whether programming for all bits for which programming has been selected has been completed or not are not made, however, it has been unable to determine suspension of programming and program-verify sequence. Therefore, in the prior art, for example, sufficient programming time has been set using a self-contained timer and programming operation and program-verify operation have been repeated in the set programming period of time. As a result, it has been required to set over programming period of time including a margin with respect to the programming period of time required for loading data in the memory cells.
Further, when the detection and determination operation on termination of programming is made to be executed by a CPU in a system located outside a semiconductor nonvolatile memory device (for example, a portable system such as an automatically controlled camera system, a portable recorder and a pocket computer), it is required to have buses between the semiconductor nonvolatile memory device and the system always kept connected in order to transfer the memory cell data in the semiconductor nonvolatile memory device to the CPU. Thus, there has been such a problem that the CPU is occupied by reprogramming control of the semiconductor volatile memory device at time of loading data.
It is a first object of the present invention to solve the above-mentioned problems and to provide a semiconductor nonvolatile memory device capable of executing electrical programming and erasing of sector information while keeping the buses between the semiconductor nonvolatile memory device and the system separated.
Further, the prior art described above has been effective only when (1) the threshold voltages of the memory cells are brought to a high voltage state selectively from a low voltage state after erase by programming operation and (2) 0V is applied to programming-selected drain lines and positive voltage is applied to unselected drain lines as shown at a in FIG. 19. However, when (1) the threshold voltages of the memory cells are brought to a low voltage state selectively from a high voltage state after erase by programming operation and (2) positive voltage is applied to programming-selected drain lines and 0V is applied unselected drain lines at programming time as shown at b in FIG. 19, it has been impossible to control continuation and suspension of programming of memory cells.
The reason thereof will be explained with reference to FIG. 20. FIG. 20 shows the state of memory cells on the word line on the way of programming and program-verify sequence.
Now, it is assumed that the threshold voltages of memory cells connected to data lines b1 and b2 are in a high voltage state and the threshold voltages of memory cells connected to data lines b3 and b4 are in a low voltage state. Those data that are desired to be loaded in respective memory cells are shown as initial loaded data. Since the memory cell connected to the data line b2 has a high threshold voltage in the present state, it is required to repeat programming further. Since the memory cell of a data line b4 has a low threshold voltage, programming operation from the next time is suspended.
In the verify system which is a conventional system, all data lines are precharged regardless of the latch data of a data hold circuit corresponding to the read/write circuit shown in FIG. 22. Then, when read voltage is applied to the word lines, voltages the data lines b3 and b4 having the memory cells of a low threshold voltage become 0V. Since the latch data of the data hold circuit are reloaded by using this state of the data lines, and thereafter, data lines are charged in accordance with the latched data, the data lines b2 and b4 and the data line b1 holding precharge voltage show 3V by initial loaded data of the data hold circuit. Thus, reloaded data become different in the data line b4 desirous to suspend reprogramming and the data line b1 desirous to hold initial loaded data 0V. Namely, it is impossible to use the verify system which is a conventional system for a memory system shown at b in FIG. 19.
It is a second object of the present invention to determine continuation and suspension of the programming and program-verify sequence with respect to each data line and to determine the fact that programming of all memory cells which become objects of programming has been completed in the interior of a semiconductor nonvolatile memory device in the semiconductor nonvolatile memory device when a programming threshold voltage of a semiconductor nonvolatile memory element (memory cell) is brought to a low voltage state selectively from a high voltage state after erase by programming operation, and the selected drain line is made to show positive voltage and the unselected drain line voltage is made to show 0V at time of programming.
In order to achieve the above-mentioned object, the present invention has a structure shown hereunder.
Namely, nonvolatile semiconductor memory cells each having a control gate, a floating gate, a drain and a source are arranged in an array form, a plurality of memory cells in which control gates are connected in common by means of a word line are formed as a sector, the drains of memory cells in the sector are connected to different data lines, at least a precharging circuit, a state detecting circuit and a data hold circuit are provided for each data line, the word line is connected to a row address decoder, and the precharging circuit and the state detecting circuit are connected to a control signal generating circuit.
In the semiconductor nonvolatile memory device of the present invention, at least one word line is selected by a row address decoder and positive voltage is applied thereto, thereby to perform electrical erase at the same time for a plurality of memory cells in which the control gates are connected to the word line. Further, after the data which are to be loaded in the memory cells are transferred to the data hold circuit provided along each data line, negative voltage is applied to the selected word line using the row address decoder, and the voltage in accordance with the data in the data hold circuit is applied to the data line, thereby to perform programming operation. Namely, collective electrical erase and programming for the sector with the word line described above as a unit are possible. After programming operation described above, the operation of reading out the states of the memory cells in the sector at the same time (collective verify) is performed by applying voltage to the data lines selectively through the precharging circuit in accordance with the data in the data hold circuit, and following to the verify described above, the data in the data hold circuit corresponding to the memory cells in the sector are detected at the same time (state detecting operation) using the state detecting circuit, and the programming operation, the collective verify operation and the state detecting operation are continued until loading to the memory cells is completed.